2.0D, 2.2D, 2.1D, 2.3D Integrated Substrate Provider

No through vias(TSVs, TLVs..) required.

No solders required between interposer / substrate / PCB.

One Integrated Substrate can replace the combination of silicon interposer and substrate.

Meet functional requirements and simplifies the manufacturing logistic.

Quick product prototyping.


SiPlus is developing system integration technologies and products that meet functional requirement with less impact to the environment.


1. ECTC 2023 Conference

Chia-Peng Sun, et al., “Optimization of 2.2D Underfill Process by Novel Methodology and Direct Observation of Capillary Underfill Process”.

2. ICEP 2023 Conference

Dyi Chung Hu, et al., “In-situ observation of underfill dispensing process”. L. H. Shen, et al., “Predicting Void Reduction of Flip Chip Package in the Pressure Oven”.

3. WLPS 2023 Conference

Dyi Chung Hu, et al., “Method of doubling the wafer level RDL layers in 2.2D and RDL Substrate”.

4. ECTC 2022 Conference

Dyi Chung Hu, et al., “A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications”.

5. Chip Scale Review, 2022 March Issue

Dyi Chung Hu, SR 2022 paper, “2.2D Die last Integrated Substrate for Heterogeneous Integration Applications”.

6. ECTC 2021 conference paper on 2.2D

Dyi Chung Hu, et. al. "2.2D Die last Integrated Substrate for High Performance Applications".

7. IMAPS 2020 Conference Paper on 2.0D

D.C. Hu and James Ho "Methods to Reduce the Hierarchy of Interconnections in Electronic System".

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