Chia-Peng Sun, et al., “Optimization of 2.2D Underfill Process by Novel Methodology and Direct Observation of Capillary Underfill Process”.
Dyi Chung Hu, et al., “In-situ observation of underfill dispensing process”. L. H. Shen, et al., “Predicting Void Reduction of Flip Chip Package in the Pressure Oven”.
Dyi Chung Hu, et al., “Method of doubling the wafer level RDL layers in 2.2D and RDL Substrate”.
Dyi Chung Hu, et al., “A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications”.
Dyi Chung Hu, SR 2022 paper, “2.2D Die last Integrated Substrate for Heterogeneous Integration Applications”.
Dyi Chung Hu, et. al. "2.2D Die last Integrated Substrate for High Performance Applications".
D.C. Hu and James Ho "Methods to Reduce the Hierarchy of Interconnections in Electronic System".